Architectural Optimizations in Multi-core Processors: Improving Thread-based Synchronization and Communications

The quest for greater computational power isnever-ending. Recently, the architectural trend hasshifted from improving single-threaded applicationperformance to improving multi-threaded applicationperformance. Thus, multi-core processors have beenincreasingly popular. To achieve concurrent executionof threads on multi-core processors, applicationsmust be explicitly restructured to exploitparallelism, either by programmers or compilers. However, conventional parallel programming models mayintroduce overhead due to synchronization andcommunications among threads in multi-threadedapplications. This book presents three architecturaloptimizations to improve thread-based synchronizationand communications support in multi-core processors. Register-Based Synchronization (RBS) uses hardwareregisters efficiently to provide synchronizationsupport in multi-core processors. Prepushing is asoftware controlled data forwarding technique toprovide communications support in multi-coreprocessors. Software Controlled Eviction (SCE) improves shared cache communications by placingshared data in shared caches.